Digital Image Blending Using Inaccurate Addition

Inaccurate computing is found to be a high-speed, low-power and energy-efficient alternative accurate for error-tolerant applications. In this context, paper analyzes the usefulness of inaccurate digital image processing application, viz. blending, which has been less explored. We analyze use addition blending used in applications such as photo editing computer graphics. For experimentation, we considered two images using separately. many architectures are suitable implementation both FPGA ASIC design environments perform comparative analysis. that an with optimum inaccuracy produces similar quality blended obtained addition. The quantified standard metrics peak signal-to-noise ratio structural similarity index measure. particular, adder, M-HERLOA, was preferable from combined perspectives image, error metrics. implemented adders corresponding environments. Xilinx Artix-7 FPGA-based 32/28 nm CMOS cell library type cell-based implementation. results show that, implementation, M-HERLOA enables reduction delay by 13%, requires 50% fewer LUTs 49% registers consumes 24.3% on-chip power compared high-speed adder while yielding good quality. 64.6% (24.4%), 43% (82.4%), area dissipates 63% (67.8%) than carry ripple (carry look-ahead adder).